module dequeuePortDeMuxer32 (
    input wire clk,
    input wire rst,
    input wire dequeue_vld_in,                 //出栈使能
    input wire [5:0] dequeue_priority_in,
    input wire [7:0] is_last_head_in,          //判断是否为此队列的最后一个元素
    input wire [15:0] dequeue_head_old_in,     //出队的旧队头
    output reg [31:0] dequeue_vld_out,
    output reg [5:0] dequeue_priority_out [0:31],
    output reg [7:0] is_last_head_out [0:31],
    output reg [9:0] dequeue_head_old_out [0:31]
);
    integer i;

    always @(posedge clk) begin
        if (rst) begin
            //复位信号拉高时，将所有的使能信号拉低
            dequeue_vld_out <= 32'h00000000;
            for (i=0; i<32; i=i+1) begin
                is_last_head_out[i] <= 0;
                dequeue_head_old_out[i] <= 0;
            end
        end
        else begin
            if (dequeue_vld_in) begin
                dequeue_vld_out <= (1 << dequeue_head_old_in[15:10]);
                is_last_head_out[dequeue_head_old_in[15:10]] <= is_last_head_in;
                dequeue_priority_out[dequeue_head_old_in[15:10]] <= dequeue_priority_in;
                dequeue_head_old_out[dequeue_head_old_in[15:10]] <= dequeue_head_old_in[9:0];
            end
            else begin
                dequeue_vld_out <= 32'h00000000;
            end
        end
    end
    
endmodule